Multi-core Demands Multi-Interfaces

 

Yale N. Patt

The University of Texas at Austin

 

ABSTRACT

 

The challenge for the microarchitect has always been (with very few notable domain-specific exceptions) how to translate the continually increasing processing power provided by Moore's Law into increased performance, or more recently into similar performance at lower cost in energy.  The mechanisms in the past (almost entirely) kept the interface intact and used the increase in transistor count to improve the performance of the microarchitecture of the uniprocessor.  When that became too hard, we went to larger and larger on-chip caches.  Both are consistent with the notion that "abstractions are good."  At some point, we got overwhelmed with too many transistors; predictably, multi-core was born.  As the transistor count continues to skyrocket, we are faced with two questions: what should be on the chip, and how should the software interface to it.  If we expect to continue to take advantage of what process technology is providing, I think we need to do several things, starting with rethinking the notion of abstraction and providing multiple interfaces for the programmer. 

 

BIO

 

Yale Patt is a teacher at The University of Texas at Austin who directs the research of eight PhD students in computer architecture, while continuing to consult in the microprocessor industry.  He enjoys equally teaching the required intro to computing course to 400+ freshmen every other fall, and the advanced graduate course in microarchitecture every other spring.  He has earned appropriate degrees from reputable universities and more than enough awards for his research and teaching.  More detail is available on his web site: http://www.ece.utexas.edu/~patt.