The 15th International Symposium on

Welcome to HPCA-15

Conference Program

 

 

 

High-Performance Computer Architecture

Raleigh, North Carolina - February 14-18, 2009

Monday, February 16, 2009

7:30am - 8:30am

Breakfast

8:30am - 8:50am

Welcome Messages

8:50am - 10:00am

Keynote Session I

Chair: Tom Conte, Georgia Tech

An Intelligent IT Infrastructure for the Future (abstract)

Prith Banerjee, Senior V.P. of Research and Director, HP Labs

10:00am - 10:30am

Break

10:30am - 12:00pm

SESSION 1: BEST PAPER NOMINEES

Chair: Josep Torrellas, UIUC

Techniques for Bandwidth-Efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems

Eiman Ebrahimi, University of Texas at Austin

Onur Mutlu, Carnegie Mellon University

Yale Patt, University of Texas at Austin

 

Voltage Emergency Prediction: Using Signatures to Reduce Operating Margins

Vijay Janapa Reddi, Harvard University

Meeta Gupta, Harvard University

Glenn Holloway, Harvard University

Gu Yeon Wei, Harvard University

Michael D. Smith, Harvard University

David Brooks, Harvard University

 

A Low-Radix and Low-Diameter 3D Interconnection Network Design

Yi Xu, University of Pittsburgh

Yu Du, University of Pittsburgh

Bo Zhao, University of Pittsburgh

Xiuyi Zhou, University of Pittsburgh

Youtao Zhang, University of Pittsburgh

Jun Yang, University of Pittsburgh

 

12:00pm - 1:30pm

Lunch

1:30pm - 3:30pm

SESSION 2A: MULTICORE CACHE ARCHITECTURES

Chair: Gabriel Loh, Georgia Tech

Adaptive Spill-Receive for Robust High-Performance Caching in CMPs

Moinuddin K. Qureshi, IBM Research

 

Design and Implementation of Software-Managed Caches for Multicores with Local Memory

Sangmin Seo, Seoul National University

Jaejin Lee, Seoul National University

Zehra Sura, IBM Research

 

In-Network Snoop Ordering (INSO): Snoopy Coherence on Unordered Networks

Niket Agarwal, Princeton University

Li-Shiuan Peh, Princeton University

Niraj Jha, Princeton University

 

Practical Off-chip Meta-data for Temporal Memory Streaming

Thomas Wenisch, University of Michigan

Michael Ferdman, Carnegie Mellon University

Anastasia Ailamaki, Carnegie Mellon University

Babak Falsafi, EPFL

Andreas Moshovos, University of Toronto

SESSION 2B: RELIABILITY

Chair: Todd Austin, Univ. of Michigan

Soft Error Vulnerability Aware Process Variation Mitigation

Xin Fu, University of Florida

Tao Li, University of Florida

Jose Fortes, University of Florida

 

Accurate Microarchitecture-Level Fault Modeling for Studying Hardware Faults

Man-Lap Li, University of Illinois, Urbana-Champaign

Pradeep Ramachandran, University of Illinois, Urbana-Champaign

Ulya R. Karpuzcu, University of Illinois, Urbana-Champaign

Siva Kumar Sastry Hari, University of Illinois, Urbana-Champaign

Sarita V. Adve, University of Illinois, Urbana-Champaign

 

Eliminating Microarchitectural Dependency from Architectural Vulnerability

Vilas Sridharan, Northeastern University

David R. Kaeli, Northeastern University

 

Versatile Prediction and Fast Estimation of Architectural Vulnerability Factor from Processor Performance Metrics

Lide Duan, Louisiana State University

Bin Li, Louisiana State University

Lu Peng, Louisiana State University

3:30pm - 4:00pm

Break

4:00pm - 5:30pm

Panel (joint with PPoPP): Opportunities Beyond Single-Core Microprocessors (abstract) (panel presentation slides)

Moderator: Mark Hill, Univ. of Wisconsin, Madison

Panelists:

Sarita V. Adve, UIUC

David A. Bader, Georgia Tech

William Dally, Stanford Univ.

William Harrod, DARPA

Vivek Sarkar, Rice Univ.

5:30pm - 6:00pm

Break

6:30pm - 7:30pm

TCCA Business Meeting

6:00pm - 8:00pm

Reception

 

 

Tuesday, February 17, 2009

7:30am - 8:50am

Breakfast

8:50am - 10:00am

Keynote II (joint with PPoPP)

Chair: Yan Solihin, NC State Univ.

Multi-core Demands Multi-Interfaces (abstract) (slides)

Yale Patt, University of Texas at Austin

10:00am - 10:30am

Break

10:30am - 12:00pm

SESSION 3A: ON-CHIP NETWORKS-I

Chair: Timothy M. Pinkston, USC

Elastic Buffer Flow Control for On-Chip Networks

George Michelogiannakis, Stanford University

James Balfour, Stanford University

William J. Dally, Stanford University

 

Express Cube Topologies for On-Chip Interconnects

Boris Grot, University of Texas at Austin

Joel Hestness, University of Texas at Austin

Onur Mutlu, Carnegie Mellon University

Stephen W. Keckler, University of Texas at Austin

 

Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs

Reetuparna Das, Pennsylvania State University

Soumya Eachempati, Pennsylvania State University

Asit K. Mishra, Pennsylvania State University

Vijaykrishnan Narayanan, Pennsylvania State University

Chita Das, Pennsylvania State University

 

SESSION 3B: PROCESSOR MICROARCHITECTURE-I

Chair: Eren Kursun, IBM T.J. Watson Research

Architectural Contesting

Hashem Hashemi Najaf-abadi, NC State University

Eric Rotenberg, NC State University

 

Lightweight Predication Support for Out of Order Processors

Mark Stephenson, IBM Research

Lixin Zhang, IBM Research

Ram Rangan, IBM Research

 

BlueShift: Designing Processors for Timing Speculation from the Ground Up

Brian Greskamp, University of Illinois, Urbana-Champaign

Lu Wan, University of Illinois, Urbana-Champaign

Ulya R. Karpuzcu, University of Illinois, Urbana-Champaign

Jeffrey J. Cook, University of Illinois, Urbana-Champaign

Josep Torrellas, University of Illinois, Urbana-Champaign

Deming Chen, University of Illinois, Urbana-Champaign

Craig Zilles, University of Illinois, Urbana-Champaign

 

12:00pm - 1:30pm

Lunch

1:30pm - 3:30pm

SESSION 4A: NUCA AND 3D STACKED MEMORY HIERARCHIES

Chair: Doug Burger, Microsoft Research

PageNUCA: Selected Policies for Page-grain Locality Management in Large Shared Chip-multiprocessor Caches

Mainak Chaudhuri, Indian Institute of Technology, Kanpur

 

A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs

Guangyu Sun, Penn State University

Xiangyu Dong, Penn State University

Yuan Xie, Penn State University

Jian Li, IBM

Yiran Chen, Seagate Tech

 

Dynamic Hardware-Assisted Software-Controlled Page Placement to Manage Capacity Allocation and Sharing within Large Caches

Manu Awasthi, University of Utah

Kshitij Sudan, University of Utah

Rajeev Balasubramonian, University of Utah

John Carter, University of Utah

 

Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy

Niti Madan, University of Utah

Li Zhao, Intel

Naveen Muralimanohar, University of Utah

Aniruddha Udipi, University of Utah

Rajeev Balasubramonian, University of Utah

Ravishankar Iyer, Intel

Srihari Makineni, Intel

Donald Newell, Intel

 

SESSION 4B: POWER/PERFORMANCE-EFFICIENT ARCHITECTURES AND ACCELERATORS

Chair: David Brooks, Harvard University

Reconciling Specialization and Flexibility Through Compound Circuits

Sami Yehia, Thales Research & Technology

Sylvain Girbal, Thales Research & Technology

Hugues Berry, INRIA

Olivier Temam, INRIA

 

CAMP: A Technique to Estimate Per-Structure Power at Run-time using a Few Simple Parameters

Michael D. Powell, Intel

Arijit Biswas, Intel

Joel Emer, Intel

Shubhendu S. Mukherjee, Intel

Basit R. Sheikh, Cornell

Shrirang Yardi, Virginia Tech

 

Variation-Aware Dynamic Voltage/Frequency Scaling

Sebastian Hebert, Carnegie Mellon University

Diana Marculescu, Carnegie Mellon University

 

Bridging the Computation Gap Between Programmable Processors and Hardwired Accelerators

Kevin Fan, University of Michigan

Manjunath Kudlur, University of Michigan

Ganesh Dasika, University of Michigan

Scott Mahlke, University of Michigan

 

3:30pm - 4:00pm

Break

4:00pm - 5:30pm

Industrial Perspectives Panel (joint with PPoPP) (abstracts)

Moderator: Partha Ranganathan, HP Labs

Panelists:

Rick Hetherington, Sun

David Luebke, Nvidia

Moinuddin Qureshi, IBM T.J. Watson Research

Daniel Reed, Microsoft Research

5:30pm - 6:30pm

Break

6:30pm

Conference Excursion

 

 

Wednesday, February 18, 2009

7:30am - 9:00am

Breakfast

9:00am - 10:00am

SESSION 5A: PERFORMANCE MODELING AND ANALYSIS

Chair: Olivier Temam, INRIA

A First-Order Fine-Grained Multithreaded Throughput Model

Xi E. Chen, University of British Columbia

Tor M. Aamodt, University of British Columbia

 

Characterization of Direct Cache Access on Multi-core Systems and 10GbE

Amit Kumar, Intel

Ram Huggahalli, Intel

Srihari Makineni, Intel

 

SESSION 5B: ON-CHIP NETWORKS-II

Chair: Jun Yang, Univ. of Pittsburgh

MRR: Enabling Fully Adaptive Multicast Routing for CMP Interconnection Networks

Pablo Abad Fidalgo, University of Cantabria

Valentin Puente Varona, University of Cantabria

Jose Angel Gregorio Monasterio, University of Cantabria

 

Prediction Router: Yet Another Low Latency On-Chip Router Architecture

Hiroki Matsutani, Keio University

Michihiro Koibuchi, National Institute of Informatics

Hideharu Amano, Keio University

Tsutomu Yoshinaga, The University of Electro-Communications

 

10:00am - 10:30am

Break

10:30am - 12:00pm

SESSION 6A: SECURITY, VERIFICATION, AND VALIDATION

Chair: Youtao Zhang, Univ. of Pittsburgh

Fast Complete Memory Consistency Verification (slides+audio)

Yunji Chen, Chinese Academy of Sciences

Yi Lv, Chinese Academy of Sciences

Tianshi Chen, University of Science and Technology of China

Haihua Shen, Chinese Academy of Sciences

Pengyu Wang, Chinese Academy of Sciences

Hong Pan, Chinese Academy of Sciences

Weiwu Hu, Chinese Academy of Sciences

 

Hardware-Software Integrated Approaches to Defend Against Software Cache-based Side Channel Attacks

Jingfei Kong, University of Central Florida

Onur Aciicmez, Samsung Information Systems America

Jean-Pierre Seifert, Samsung Information Systems America

Huiyang Zhou, University of Central Florida

 

DACOTA: Post-silicon Validation of the Memory Subsystem in Multi-core Designs

Andrew DeOrio, University of Michigan

Ilya Wagner, University of Michigan

Valeria Bertacco, University of Michigan

 

SESSION 6B: PROCESSOR MICROARCHITECTURE-II

Chair: Eric Rotenberg, NC State Univ.

Criticality-Based Optimizations for Efficient Load Processing

Samantika Subramaniam, Georgia Institute of Technology

Anne C. Bracy, Intel

Hong Wang, Intel

Gabriel H. Loh, Georgia Institute of Technology

 

iCFP: Tolerating All Level Cache Misses in In-Order Processors

Andrew Hilton, University of Pennsylvania

Santosh Nagarakatte, University of Pennsylvania

Amir Roth, University of Pennsylvania

 

Feedback Mechanisms for Improving Probabilistic Memory Prefetching

Ibrahim Hur, IBM

Calvin Lin, University of Texas at Austin

 

12:00pm - 1:00pm 

Keynote III (joint with PPoPP)

Chair: Keshav Pingali, Univ. of Texas at Austin

How to Build Programmable Multi-Core Chips (abstract)

Jack Dennis, MIT

1:00pm - 1:30pm

Best paper presentation and closing remarks